This invention relates to an improved parallel test circuit used to shorten the test time of a semiconductor memory device, and more particularly to a parallel test circuit that can perform the parallel test and data reading at the same time. By using the test circuit of the present invention whose circuit is less complicated than the conventional one, the test time is shortened and the test accuracy improved.
Generally, as the integration of the memory device increases to 4 Mega bit, 16 Mega bit, and 64 Mega bit, and so forth, the test time for the memory device also increases. Accordingly, a parallel test method that tests several bits simultaneously in order to shorten the test time is used. A parallel test is performed by storing "1" (high) or "0" (low) at the same time onto the several cells that have been selected to test and then by reading them at the same time to see whether the same data as stored are read out. For example, if all the data are found to be "1"s when reading the cells after storing "1"s onto all the cells that had been selected, the test is evaluated as "pass". If any of the data are read as "0"s, the test is evaluated as "fail".
Up to now, a logic circuit has been used when carrying out a test on the memory device described above. For example, a 16 bit parallel test circuit illustrated in FIG. 1 has been used when testing 16 Mega DRAM. In the conventional parallel test circuit illustrated in FIG. 1, 16 data D1 through D16, each of which is 1 bit data, are divided into four groups of input IN1 to IN4 with each group having 4 data, and then are input into the logic circuit for testing. Then first, four data of each group of input IN1 through IN4 are compared with each other to see whether they are the same, and then they are output as final outputs after comparing theix outputs again. However, as described previously, the disadvantages of the conventional method are that it takes too long to compare the data under all given conditions and that many transistors must be used in order to carry out the test successfully. Also, an accurate error check is impossible since the data of input IN1 and data of input IN2 are not compared with each other even though the data D1, D2, D3, and D4 are compared through input IN1 and the data D5, D6, D7, and D8 are compared through input IN2.